In the process of testing a semiconductor, electrical continuity of the semiconductor in a state of a semiconductor wafer before being diced is tested by contacting a conductive probe with the semiconductor wafer and a defective piece is sometimes detected (WLT: Wafer Level Test). When conducting the WLT, a probe card that contains many probes is used to deliver test signals from test equipment (tester) to the semiconductor wafer. Generally, in the WLT, each probe is made to contact each die when scanning the die on the semiconductor wafer with the probe card. However, because hundreds to tens of thousands of dies are present on one semiconductor wafer, it takes considerably long time for testing one semiconductor wafer, and an increase in the number of dies causes an increase in cost.
To take care of this issue, recently, a method called FWLT (Full Wafer Level Test) is used. In the FWLT, the probes are collectively contacted with all the dies on the semiconductor wafer or at least about ¼ to ½ of dies on the semiconductor wafer (for example, see Patent document 1). In the FWLT, the tip of each probe must contact with a fine electrode pad of the semiconductor wafer, and this requires a technology for increasing accuracy of positioning the tips of the probes and for aligning the probe card with the semiconductor wafer.
FIG. 13 is a schematic diagram of one example of structure of a probe card used in the FWLT. A probe card 51 as shown in the figure includes a plurality of probes 52 provided corresponding to a layout pattern of electrode pads on the semiconductor wafer, a probe head 53 that holds the probes 52, a space transformer 54 that transforms a fine wiring pattern in the probe head 53 into a wiring pattern in a wider space, an interposer 55 that relays a wiring extended from the space transformer 54, and a substrate 57 that further increases the space of the wiring 56 relayed by the interposer 55 and connects the wiring 56 to a terminal of the test equipment.
In the probe card 51 structured as explained above, the space transformer 54 serves also as a function of reducing a difference between the coefficient of thermal expansion of the semiconductor wafer and the coefficient of thermal expansion of the substrate 57, and occurrence of displacement is thereby prevented upon testing in a high temperature environment.
Patent document 1: Japanese Patent Application Laid-Open No. 2003-240801